Thermal Margin Is RF Margin: Why PA Performance Fails at High Junction Temperature

A 10 W RF PA at 40% PAE is also a 15 W heater.

At 20% PAE, that same 10 W output can generate ~40 W heat.

That heat does not disappear inside the RF link budget. It moves through the die, package, PCB, TIM, and heatsink. Then temperature feeds back into gain, compression, phase, and reliability.

For Phased Arrays, spatial temperature gradients add another failure mechanism. This is why PA thermal design is fundamentally RF system design.

Start With the Real PA Power Balance

Power-added efficiency is:

PAE = (POUT − PIN) / PDC

Therefore:

PDC = (POUT − PIN) / PAE

Power dissipated inside the PA becomes:

PDISS = PDC + PIN − POUT

Analog Devices uses this same power-balance approach when calculating RF-amplifier junction temperature. [Ref. 1]

For a high-gain PA, PIN is usually relatively small.

Then:

PDISS ≈ POUT(1/PAE − 1)

That equation should appear in every PA thermal review.

What PAE Really Means Thermally

Consider:

POUT = 10 W

Ignoring small input power:

The RF output remains exactly 10 W, but heat generation changes by 4x between 50% and 20% PAE.

That is why efficiency becomes a thermal specification. Not simply an RF performance metric.

The First Thermal Equation Is Useful—But Often Misused

The familiar first-order relationship is:

TJ = TA + PDISS · θJA

Suppose:

• Ambient temperature = 55°C

• Dissipated power = 8 W

• Effective thermal resistance = 6°C/W

Then, ΔT = 8 × 6 = 48°C and TJ ≈ 103°C

The arithmetic is correct. The danger lies in treating θJA as universal.

For RF PAs, θJA Is Often the Wrong Starting Metric

Junction-to-ambient thermal resistance depends strongly on:

• PCB design

• airflow

• board construction

• enclosure

• heatsinking

Analog Devices explicitly notes θJA depends on the entire system environment. [Ref. 2]

For exposed-pad RF amplifiers, heat flows mainly through the package underside.

Analog Devices therefore identifies θJC as the more useful PA metric. [Ref. 3]

A better first-order thermal chain is:

TJ = TC + PDISS · θJC

with:

TC = TA + PDISS · θCA

Therefore:

TJ ≈ TA + PDISS(θJC + θCA)

where θCA represents the downstream assembly path. That path includes much more than the package.

The Complete Thermal Network Is an RF Hardware Stack-Up

Heat can travel through:

Die → die attach → package slug → solder → PCB → vias → TIM → heatsink

Analog Devices models these elements as series-and-parallel thermal resistances. [Ref. 3]

The basic conduction resistance is:

RTH = L/(kA)

where:

• L = heat-flow length

• k = thermal conductivity

• A = cross-sectional area

That equation explains almost every practical PA cooling improvement. Shorten the heat path, increase area, increase thermal conductivity, then remove interface resistance.

Pain Point 1: Peak PAE Can Hide the Real Thermal Operating Point

Power amplifiers rarely transmit continuous unmodulated maximum power.

Modern 5G signals have large envelope variations. Radar often operates pulsed. Satellite transmitters can move between power states.

Therefore, thermal design needs waveform-dependent dissipation.

Back-Off Efficiency Can Determine the Real Heat Load

A 38 GHz silicon Doherty PA achieved 15% PAE at 6 dB back-off. Under 200 MSym/s 64-QAM, it reported 12.2% average PAE. Its measured average output power was approximately 20 dBm. [Ref. 4]

This illustrates a critical thermal-design rule.

Do not size cooling from Psat efficiency alone. The real waveform determines average dissipation.

This Is Becoming More Important in Commercial mm-Wave

A 2026 IEEE review discusses recent mm-Wave CMOS PA architectures. It reports recent Doherty designs exceeding 16.8% linear PAE. Those architectures are already used within commercial 5G FR2 RFICs. [Ref. 5]

Low absolute RF power does not eliminate thermal density. Hundreds of channels can occupy a small aperture.

That converts device heating into a system-level temperature field.

A Real 28 GHz MMIC Shows the Temperature Margin

Analog Devices' HMC863ALC4 operates across 24–29.5 GHz. It provides approximately 24 dB gain and +28.5 dBm Psat. Its specified PAE is approximately 22.5%. [Ref. 6]

Its channel-to-ground-paddle thermal resistance is 31.2°C/W. At an 85°C reference temperature, nominal junction temperature is 145.06°C. The permitted maximum junction temperature is 175°C. [Ref. 7]

That leaves only about 30°C junction margin under those specified conditions.

That is why mm-Wave thermal design cannot be postponed.

The Same PA Also Shows RF Temperature Sensitivity

The HMC863ALC4 specifies gain variation around 0.03 dB/°C. [Ref. 7]

A simple 60°C temperature excursion therefore corresponds to roughly 0.03 × 60 ≈ 1.8 dB using that first-order coefficient.

The actual response need not remain perfectly linear, but the magnitude is already architecturally significant.

A thermal problem can therefore become an EIRP problem.

Pain Point 2: Thermal Resistance Is Not Always a Constant

Engineers often treat θJC as a fixed resistor. Real semiconductor thermal behaviour is more complicated.

Material thermal conductivity varies with temperature. Transient operation also changes effective thermal response.

Qorvo's GaN thermal measurements demonstrate both effects clearly. [Ref. 8]

A Powerful Pulsed-versus-CW Benchmark

Qorvo evaluated a GaN device dissipating 44.7 W during each RF pulse. Case temperature was 85°C.

For 100 µs pulses at 10% duty cycle, TCH,max ≈ 150°C and θJC ≈ 1.45°C/W.

Under CW operation, TCH,max ≈ 177.8°C and θJC ≈ 2.08°C/W. [Ref. 8]

Same nominal pulse power, but very different thermal condition.

Duty Cycle Cannot Be Reduced to Average Power Alone

The Qorvo example shows pulse width matters and thermal time constants matter. [Ref. 8]

This becomes critical in Radar hardware. A 10% duty-cycle transmitter is not thermally equivalent to CW. But neither is it equivalent to simply applying 10% average heat.

Short-time junction peaks can still become significant. Therefore, pulsed RF needs transient thermal simulation.

GaN Adds Another Measurement Trap

An IR camera does not directly see maximum GaN channel temperature. The active channel sits beneath the visible die surface.

NXP therefore derives GaN channel temperature using FEA thermal modelling. The model is validated against IR surface-temperature measurements. [Ref. 9]

That distinction is extremely important.

A pretty thermal-camera image is not necessarily TJ.

A Current 2026 GaN Benchmark Shows How Close Margins Can Become

NXP's A5G26H606W19N data sheet is dated February 2026. The device permits a maximum channel temperature of 225°C. [Ref. 10]

Its Carrier channel-to-case thermal resistance is 1.3°C/W at approximately 62 W dissipated power. The associated case temperature is approximately 122°C.

A first-order calculation gives TCH ≈ 122 + 62 × 1.3

Therefore, TCH ≈ 203°C.

That leaves only approximately 22°C margin to the 225°C maximum.

This is why high-power GaN lives or dies thermally.

Thermal Data Has Measurement Uncertainty Too

NXP characterizes RFPA thermal resistance using multiple production parts. Its reported sample sets typically contain five to ten devices. NXP reports approximately 5% combined measurement and part variation. [Ref. 11]

That matters during worst-case design. A thermal simulation matching the nominal data is not enough and design margin must absorb manufacturing variation.

Pain Point 3: In Phased Arrays, Temperature Becomes Spatial

One standalone PA can be characterized using one temperature. A large Phased Array cannot.

Centre channels can experience different cooling than edge channels. Beam states can also redistribute RF dissipation spatially.

The resulting temperature field becomes an RF-error field.

A Current mm-Wave PA Gives a Useful Temperature Coefficient

NXP's 2026 A5G18H610W19N specifies gain variation near 0.018 dB/°C from −40°C to +85°C. [Ref. 12]

Now consider a hypothetical centre-to-edge gradient ΔT = 30°C.

The corresponding first-order gain difference becomes ΔG ≈ 0.018 × 30.

Therefore, ΔG ≈ 0.54 dB

That corresponds to approximately 6.4% voltage-amplitude ratio between otherwise identical channels.

That calculation is illustrative. The temperature coefficient comes from a real 2026 mm-Wave PA.

Array Calibration Cannot Ignore Temperature

Modern Radar research explicitly identifies temperature-dependent RF-device phase errors. It also identifies online calibration as necessary during operation. [Ref. 13]

Uncorrected phase error reduces antenna gain. It can also increase sidelobe levels.

That means thermal management and RF calibration are connected. A cold calibration table does not guarantee hot-array accuracy.

Scan Angle Creates Yet Another Coupled Variable

A 2025 IEEE mm-Wave PA study examined wide-angle array loading. Active antenna mismatch exceeded approximately 4:1 VSWR in its scenario. [Ref. 14]

A conventional PA showed over 7 dB gain variation under those loads. The paper also identifies output-phase variation under changing active impedance.

Now combine load mismatch with temperature.

The PA operating point becomes:

f(frequency, power, load, bias, temperature)

That is the real phased-array problem.

Thermal Design Is More Than “Add More Vias”

Thermal vias can be extremely effective. But their performance depends on construction.

Important variables include:

• via diameter

• copper plating

• via count

• PCB thickness

• alignment

• heat-spreader area

Qorvo specifically warns that via design strongly affects PCB thermal resistance. [Ref. 15]

Via Copper Thickness Can Change Thermal Conductance Dramatically

Qorvo gives a useful 0.010-inch via example. [Ref. 15]

With two-ounce copper plating, keff ≈ 282 W/(m·K).

With half-ounce copper, keff ≈ 91 W/(m·K).

That is approximately 3.1× difference for the cited via geometry.

So “thermal via present” is not a useful specification. How the via is fabricated matters.

Stacked Heat Paths Should Remain Vertically Aligned

Qorvo recommends aligning vias through successive PCB layers. It advises against staggering them when direct downward heat flow matters. [Ref. 15]

The reasoning is straightforward.

Heat prefers the lowest-resistance conductive path. A staggered path adds lateral spreading resistance. That can produce local hot spots.

High-Frequency GaN May Need Much More Than Vias

For GaN QFN packages, Qorvo prefers thin PCBs near 0.008 inches ≈ 0.20 mm for lower thermal resistance. [Ref. 15]

It also recommends dense thermal-via arrays for high-frequency GaN MMICs.

Above approximately 1 W/mm² package-bottom heat flux, copper coin use is highly recommended. Above approximately 2 W/mm², Qorvo states copper coin should definitely be used.

That is a useful fabrication threshold.

The TIM Can Destroy an Otherwise Excellent Thermal Design

Two machined surfaces do not contact perfectly. Microscopic air gaps increase thermal resistance.

Thermal interface material fills those gaps. But TIM thickness itself adds thermal resistance.

Qorvo Gives Quantified High-Power TIM Guidance

For flange-mounted GaN devices, Qorvo recommends approximately 50–100 µm of indium or graphite interface material.

For thermal grease, it recommends approximately 25–50 µm.

Qorvo also requires at least 80% thermal-compound coverage.

Mounting pressure also matters for compressible TIM performance. [Ref. 15]

So the thermal specification needs assembly control, not simply a heatsink drawing.

Copper Coins Change the Thermal Architecture

Thermal vias conduct primarily through plated copper walls. A copper coin provides a much larger continuous metal cross-section. That reduces vertical spreading resistance substantially.

For high heat flux, the PCB becomes a mechanical thermal component. This must be decided before routing completion.

Because the coin consumes:

• routing area

• stack-up freedom

• drill space

• mechanical tolerance

Thermal architecture therefore begins during PCB architecture.

Active Cooling Is Sometimes Unavoidable

Qorvo states high-power GaN systems may require fan-cooled heatsinks. Some applications may require liquid cooling. [Ref. 15]

A 2026 thermal-management review discusses heat-pipe-assisted high-power GaN cooling. One referenced design reduced transistor temperature from 100.2°C to 68.6°C. [Ref. 16]

That is approximately 31.5% temperature reduction for that specific implementation.

Advanced cooling therefore can recover substantial thermal margin.

The Satellite Communications Problem Is Different

Spaceborne PA thermal design cannot rely on ordinary convection. In vacuum, heat moves through conduction and radiation. There is no convective heat transfer.

NASA notes enclosed spacecraft interiors are often conduction dominated. Heat rejection to space occurs primarily through radiation. [Ref. 17]

That changes the PA thermal chain fundamentally.

For LEO Payloads, Every Watt Becomes a Spacecraft Problem

A PA's dissipated power must eventually reach a radiator.

That affects:

• thermal straps

• chassis design

• radiator area

• spacecraft orientation

• power allocation

Rad-Hard layout addresses radiation reliability, it does not solve PA heat flow.

Multipactor mitigation addresses vacuum RF breakdown, it does not remove semiconductor dissipation.

These engineering problems coexist.

Rigid-Flex RF Adds Another Thermal Constraint

Flexible antenna and RF electronics increasingly integrate active components.

A 2025 review identifies PAs as major local heat sources in flexible arrays. The review also notes flexible substrates can limit heat dissipation. [Ref. 18]

That creates a classic Rigid-Flex RF conflict. The mechanically desirable material may be thermally undesirable.

The thermal transition must therefore be engineered explicitly.

Thermal Gradients Can Also Distort Matching Networks

Matching components possess temperature coefficients. PCB dielectric properties change with temperature.

Copper dimensions also expand. Device optimum impedance changes with operating condition.

Therefore, the PA matching network does not remain perfectly stationary.A room-temperature Smith-chart match is only one operating state.

The Bias Network Can Become Thermally Coupled Too

GaN drain and gate bias define PA operating point. Temperature changes transistor characteristics.

Bias control then influences:

• gain

• current

• PAE

• linearity

• heat generation

This creates electrothermal feedback.

A thermal model and an RF model should therefore use consistent bias states.

The Strategic Engineering Solution

Top-tier PA development should use electrothermal co-design, not sequential RF design followed by heatsink selection.

1. Calculate Heat From the Real RF Waveform

Start from:

PDISS = PDC + PIN − POUT − PREF

NXP uses this global RF power balance in thermal characterization. [Ref. 9]

Use measured or simulated:

• PAE versus power

• back-off efficiency

• duty cycle

• modulation statistics

• reflected power

Do not use Psat efficiency everywhere.

2. Build the Complete Junction-to-Ambient Thermal Network

Model:

Junction → package → solder → PCB → coin/vias → TIM → heatsink

For exposed-pad PAs, prioritize θJC.

Analog Devices explicitly recommends this approach for RF amplifiers. [Ref. 3]

Then model the downstream assembly separately. That gives far better engineering visibility.

3. Use Transient Thermal Analysis for Radar and Burst Radios

Do not average the waveform too early.

Include:

• pulse width

• duty cycle

• repetition frequency

• burst duration

Qorvo's GaN results show duty cycle changes peak channel temperature significantly. [Ref. 8]

Thermal time constants must remain inside the model.

4. Design the PCB Heat Path Before RF Routing Is Frozen

Define:

• exposed-pad size

• via array

• copper plating

• copper coin

• internal copper spreading

• heatsink mounting

Then route around that architecture. Do not squeeze the thermal solution into leftover layout space.

5. EM-Extract the Same Hardware That Thermal Simulation Uses

Your HFSS or CST model should match the thermal geometry.

Include the same:

• copper

• vias

• packages

• ground structures

• stack-up

The electromagnetic and thermal teams should not model different boards.

That sounds obvious. It happens more often than it should.

6. Run RF Performance Across Temperature

Measure or simulate:

• gain

• S₁₁

• S₂₂

• P1dB

• Psat

• PAE

• AM-AM

• AM-PM

• EVM

• ACLR

at multiple thermal states. The PA is not qualified at 25°C alone.

7. Measure Case Temperature Where the Data Sheet Defines It

Do not place a thermocouple somewhere convenient. Use the manufacturer's thermal reference location.

NXP places case-temperature measurement beneath active device regions. [Ref. 9]

That location is deliberately linked to thermal-resistance characterization. Measurement location matters.

8. Use Multiple Temperature Measurement Methods

A thermocouple measures one physical point. An IR camera reveals surface gradients.

Embedded sensors can monitor operational temperature continuously. Qorvo recommends combining modelling with several measurement methods. [Ref. 19]

Depending on one method alone is not recommended.

9. Add On-Die Temperature Telemetry Where Available

Some Analog Devices RF PAs allow detector circuitry to monitor die temperature.

ADI demonstrates approximately 1.21 mV/°C temperature sensitivity. With a 12-bit, 2.5 V ADC, resolution is around 0.5°C/bit. [Ref. 20]

That enables thermal telemetry during real RF operation.

For active arrays, that is extremely valuable.

10. Build Temperature Into Array Calibration

Do not create one calibration table.

Create:

phase(T, f, scan, power), and:

gain(T, f, scan, power)

where system complexity justifies it.

Radar research already demonstrates operational temperature calibration importance. [Ref. 13]

For large Massive MIMO arrays, temperature should become a calibration state.

The Open RAN / Massive MIMO Consequence

Open RAN radios place many PA channels near antenna elements. That reduces feeder loss. But it concentrates thermal power near the aperture.

The thermal architecture therefore interacts with:

• antenna spacing

• beamformer location

• PA layout

• enclosure depth

• airflow

Antenna architecture and cooling architecture cannot remain independent.

The Radar Consequence

Radar PAs must often survive extreme peak output power. Yet average heat depends strongly on pulse structure.

Qorvo's pulsed GaN data demonstrates this directly. [Ref. 8]

Therefore, specify:

• peak junction temperature

• average junction temperature

• pulse thermal impedance

• duty-cycle envelope

One CW number cannot describe every Radar mission profile.

The Aerospace & Defense Consequence

Mission hardware must operate across environmental extremes. Thermal variation can change RF gain and calibration. Structural cooling choices can also influence EMC architecture.

MIL-STD-461 addresses electromagnetic compatibility rather than PA junction temperature. But PA thermal design affects the required RF and DC operating margins.

Those margins eventually affect system EMC decisions.

The B2B Procurement Implication

A supplier specification saying: “PA operates from −40°C to +85°C” is incomplete.

Ask for:

• maximum TJ or TCH

• θJC and test conditions

• PAE versus output power

• PAE versus temperature

• gain versus temperature

• P1dB versus temperature

• AM-PM versus temperature

• duty-cycle thermal limits

• mounting requirements

• TIM requirements

• heatsink reference temperature

For Phased Arrays, also request:

• channel temperature distribution

• phase versus temperature

• gain versus temperature

• recalibration requirements

For high-power GaN, request thermal-model evidence.

The Design-Review Questions I Would Ask

Before releasing a PA board:

What is the worst-case actual PDISS?

Which thermal resistance are we using?

Where is TC physically defined?

What is peak TJ under modulation?

What is TJ during prolonged back-off?

What happens after airflow degradation?

What happens at maximum ambient temperature?

What happens during worst-case VSWR?

What parameter drifts first with temperature?

If these answers are missing, the PA is not yet validated.

The Summary Takeaway

A PA should never be treated only as an RF gain block. It is simultaneously an RF source and heat source.

For high gain:

PDISS ≈ POUT(1/PAE − 1)

Therefore:

10 W at 40% PAE → ~15 W heat

while:

10 W at 20% PAE → ~40 W heat

Then:

TJ ≈ TC + PDISS·θJC

not blindly:

TJ = TA + PDISS·θJA

for every RF package.

Analog Devices specifically prioritizes θJC for exposed-pad RF amplifiers. [Ref. 3]

A current 2026 NXP GaN device allows 225°C maximum channel temperature. Its Carrier condition already calculates near 203°C channel temperature. [Ref. 10]

Meanwhile, Qorvo's pulsed example moves from 150°C to 177.8°C under CW. [Ref. 8]

So the correct question is not:

“Does the PA meet Psat at room temperature?”

It is:

“Does the complete RF channel still meet specification at real TJ?”

Because for modern RF hardware:

thermal margin is RF margin.