The penalty applies to reference-originated phase noise inside the loop.

The PLL does not magically create frequency without magnifying phase fluctuation.

A Simple Example Changes the Architecture Discussion

Suppose: N = 120

Now redesign the synthesizer so: N = 60

The reference-noise multiplication improves by:

20log₁₀(120/60) = 6.02 dB

Your original intuition is correct here. Halving N reduces reference-originated phase noise by 6.02 dB.

But there is an important second-order truth.

The PLL’s Own In-Band Noise Does Not Necessarily Improve 6 dB

A common normalized PLL noise equation is:

LPLL ≈ FOM + 10log₁₀(fPFD) + 20log₁₀(N)

Analog Devices uses this normalization for PLL in-band noise. [Ref. 2]

Suppose N halves because fPFD doubles.

Then, 20log₂ = −6.02 dB

but, 10log₂ = +3.01 dB

The net PLL-floor improvement becomes: ≈ 3.01 dB

This is a subtle but extremely important distinction.

Reference-noise contribution improves 6 dB. PLL white-noise contribution improves approximately 3 dB.

Analog Devices describes the same net improvement when doubling PFD frequency. [Ref. 3]

Pain Point 1: Large N Quietly Destroys In-Band Phase Noise

Consider a 20 GHz synthesizer.

Case A — 100 MHz PFD

N = 20 GHz / 100 MHz = 200

Reference multiplication penalty:

20log₁₀(200) ≈ 46.02 dB

Case B — 500 MHz PFD

N = 20 GHz / 500 MHz = 40

Reference multiplication penalty:

20log₁₀(40) ≈ 32.04 dB

The reference contribution improves by: ≈ 13.98 dB.

That is enormous and modern PLLs increasingly exploit this architecture.

A Current High-PFD Benchmark

Analog Devices' ADF4382A supports up to 625 MHz PFD frequency in integer mode. Its normalized in-band phase-noise floor reaches −239 dBc/Hz. [Ref. 4]

At 20 GHz, its specified integrated RMS jitter is 20 fs. Its wideband phase-noise floor reaches approximately −156 dBc/Hz at 20 GHz.

Those specifications show where modern frequency synthesis is heading.

High PFD frequency is becoming an architectural advantage.

Quantify the Same Example Using PLL FOM

Assume an idealized:

FOM = −239 dBc/Hz

At 20 GHz with fPFD = 100 MHz, N = 200

Then:

LPLL ≈ −239 + 80 + 46.02

Therefore, LPLL ≈ −112.98 dBc/Hz

Now increase: fPFD = 500 MHz, N = 40

The result becomes:

LPLL ≈ −239 + 86.99 + 32.04

Therefore, LPLL ≈ −119.97 dBc/Hz

Idealized improvement: ≈ 7 dB.

That is the expected 10log(5) improvement.

The calculation excludes reference noise, flicker, spurs, and loop peaking.

This Is Why Fractional-N Architectures Became So Important

Integer-N synthesizers tie channel spacing to PFD frequency. Fine resolution can therefore force a low PFD. That drives N upward.

Fractional-N PLLs break that restriction.

Analog Devices shows fractional-N operation enabling much higher PFD frequency. [Ref. 5]

In one ADI comparison, higher PFD operation improved phase noise by 15 dB [Ref. 1], but fractional-N operation introduces another problem: Spurs.

Fractional-N Is Not a Free Phase-Noise Upgrade

Fractional division requires time-varying divider sequences. Modern synthesizers often use sigma-delta modulation.

That moves quantization energy spectrally, but fractional spurs can still appear.

Analog Devices identifies fractional and integer-boundary spurs as key limitations. [Ref. 6]

Frequency planning therefore becomes part of phase-noise engineering.

Integer-Boundary Spurs Can Be Particularly Difficult

Suppose the fractional divide ratio approaches an integer.

Examples include 147.98 or 148.02.

Analog Devices identifies these regions as especially problematic. [Ref. 1]

Possible mitigation includes changing the reference frequency.

That shifts the problematic boundary away from the operating channel.

This is not merely firmware optimization. It is LO architecture design.

Pain Point 2: Loop Bandwidth Decides Which Noise Source Wins

A PLL is a feedback control system. Different noise sources experience different loop transfer functions.

Reference and PFD noise behave approximately Low-pass.

VCO noise behaves approximately High-pass.

Texas Instruments describes these complementary transfer functions explicitly. [Ref. 7]

That means loop bandwidth determines the dominant noise mechanism.

Inside the Loop Bandwidth

The PLL strongly controls the VCO. Reference, PFD, divider, and charge-pump noise become important.

Reference phase noise receives the 20log(N) multiplication penalty.

The VCO's free-running noise is suppressed.

Outside the Loop Bandwidth

The loop can no longer correct fast VCO fluctuations.

VCO phase noise increasingly dominates. Reference noise becomes attenuated by the loop.

TI describes this crossover behaviour in practical PLL noise models. [Ref. 7]

Therefore, loop bandwidth is not merely a lock-time parameter. It is a noise allocation parameter.

The “Best” Loop Bandwidth Is Usually Near a Noise Crossover

A common jitter-minimization strategy finds the intersection between:

PLL + reference noise and free-running VCO noise.

TI identifies this crossover as a useful minimum-jitter starting point. In one TI example, the optimum occurred near 140 kHz. [Ref. 8]

But that value belongs only to that specific system.

The principle matters more than the number.

Too Wide a Loop Can Hurt

A wider bandwidth suppresses more VCO noise.

But it passes more:

• reference noise

• PFD noise

• charge-pump noise

• fractional quantization effects

It can also worsen certain spurs.

TI explicitly identifies loop-bandwidth trade-offs among jitter, phase noise, spurs, and lock time. [Ref. 8]

Too Narrow a Loop Can Also Hurt

A narrow bandwidth strongly rejects reference-side noise, but VCO noise dominates closer to the carrier. Lock time also becomes slower.

Analog Devices recommends narrow loops specifically for clock-cleanup architectures. [Ref. 1]

That does not mean narrower is universally better. The optimum depends on the actual noise spectra.

Phase Margin Also Matters

The PLL is still a feedback system.

Poor phase margin can produce peaking near loop bandwidth. That peaking can increase phase noise around crossover.

Analog Devices recommends approximately 45°–60° as a conventional design range. [Ref. 9]

Again, the final hardware must verify the simulation.

Why Simulation Alone Can Mislead

An ideal PLL model may use:

• ideal reference oscillator

• nominal VCO gain

• ideal loop components

• noiseless supply rails

Real hardware does not.

Analog Devices recommends importing actual VCO and reference noise data. [Ref. 9]

PCB parasitics and component tolerances can change loop dynamics.

So a simulated −110 dBc/Hz result is not validation, it is a hypothesis.

A 2026 Example Shows Simulation Correlation Still Matters

An ADF4382 user reported 8–10 dB phase-noise differences versus simulation. The mismatch occurred around 1 kHz to 100 kHz offsets. That support case occurred in March 2026. [Ref. 10]

The lesson is not that simulation is unreliable. The lesson is that the complete configuration matters.

Reference source, registers, loop filter, supplies, and PCB all matter.

Pain Point 3: PLL Noise Is Often a Power-Integrity Problem

A perfect loop filter cannot rescue a contaminated VCO supply. The VCO converts supply-voltage noise into frequency modulation. This mechanism is commonly called VCO pushing.

Analog Devices notes modern PLLs can become supply-noise limited. [Ref. 11]

That statement should concern every RF layout engineer.

A Quantified LDO Example

Analog Devices compared two regulators powering an ADF4350. One regulator produced approximately 27 µV RMS noise. The lower-noise option produced approximately 9 µV RMS. [Ref. 11]

The phase-noise difference became measurable at high VCO pushing.

The lower-noise supply approached battery-powered performance. That is a very important result.

Your PLL phase-noise plot can become an LDO plot.

Power-Supply Ripple Can Create Discrete Spurs

Switching converters introduce deterministic ripple. That ripple can modulate:

• VCO supply

• charge-pump supply

• reference circuitry

The result can become discrete LO sidebands.

Analog Devices warns these spurs can violate transmitter emission requirements. [Ref. 11]

They can also degrade receiver blocking performance. Therefore, phase-noise design and SI/PI cannot remain separate.

One ADI Experiment Measured a 40–45 dB Difference

Analog Devices compared active and passive high-voltage loop-filter architectures. The high-voltage charge-pump solution reduced switching spurs by 40–45 dB. [Ref. 11]

That improvement came partly from better ripple isolation.

This is not a minor layout effect. It can determine compliance.

The Tuning Line Is One of the Most Sensitive PCB Nodes

The VCO tuning input is effectively an analog FM port. Noise here becomes frequency modulation.

Keep the loop-filter components physically close. Analog Devices specifically recommends minimizing those interconnect lengths. [Ref. 9]

The tuning trace should avoid:

• digital clocks

• switching nodes

• PA drains

• DC/DC inductors

• fast GPIO

• memory interfaces

At mm-Wave, a clean schematic can still fail through layout coupling.

Grounding Matters Too

Charge-pump current contains periodic switching components. Those currents need controlled return paths. Poor grounding can couple comparison-frequency energy into the VCO.

Analog Devices specifically recommends isolation, decoupling, and ground vias. [Ref. 12]

That connects PLL design directly to earlier PCB return-path topics.

Multiplication After the PLL Can Destroy Your Hard-Won Noise Performance

Many mm-Wave architectures generate a lower-frequency LO first. Then they multiply it.

For an ideal multiplier M:

LOUT ≈ LIN + 20log₁₀(M)

Analog Devices confirms all frequency multipliers incur this fundamental penalty. [Ref. 13]

A doubler therefore adds at least +6.02 dB.

A x4 chain adds +12.04 dB.

A x8 chain adds +18.06 dB.

A 14 GHz LO Does Not Stay Equally Clean at 28 GHz

Suppose: L14GHz = −110 dBc/Hz.

After ideal x2 multiplication, L28GHz ≈ −104 dBc/Hz, before multiplier additive noise.

Real multipliers add residual phase noise too. Analog Devices explicitly identifies this additional contribution. [Ref. 14]

So the actual result can be worse.

This Becomes Severe at 77 GHz

Suppose a 19.25 GHz source drives an ideal x4 chain.

The multiplication penalty is: 20log₁₀(4) = 12.04 dB

A source measuring −108 dBc/Hz could therefore become approximately −96 dBc/Hz before additive noise.

That number is strikingly realistic.

A Real 77 GHz Radar Benchmark

TI's AWR2944 operates from 76–81 GHz. Its phase noise is approximately −96 dBc/Hz at 1 MHz offset near 76–77 GHz. [Ref. 15]

The device uses an integrated fractional-N PLL chirp engine. That gives useful context for real mm-Wave hardware.

At 77 GHz, phase noise is not an abstract oscillator metric. It is a system specification.

Radar Is Particularly Sensitive to Close-In Phase Noise

Radar often detects weak Doppler returns beside strong clutter. Close-in oscillator noise can mask those weak returns.

Analog Devices specifically identifies radar as demanding close-in phase-noise performance. [Ref. 16]

Critical offsets can extend from roughly 1 kHz to 1 MHz. [Ref. 17]

That overlaps the region where PLL architecture matters most.

Why Phase Noise Hurts Receivers

Consider a strong adjacent interferer. The LO contains phase-noise sidebands.

Mixing transfers those sidebands around the interferer. The resulting noise can overlap the desired weak channel.

Analog Devices describes this classic reciprocal-mixing mechanism. [Ref. 18]

A better LNA cannot fix a noisy LO.

Why Phase Noise Hurts OFDM and 5G

OFDM relies on orthogonality between subcarriers. Rapid phase fluctuation destroys that orthogonality.

The consequences include:

• common phase error

• intercarrier interference

• EVM degradation

• constellation rotation

IEEE research identifies phase noise as a serious OFDM degradation mechanism. [Ref. 19]

That makes the PLL part of the EVM budget.

Phase Noise and Jitter Are Related, But Not Identical

Integrated phase noise gives RMS phase error.

For integrated SSB phase noise A:

σφ ≈ √(2·10^(A/10))

Then RMS time jitter is:

σt = σφ/(2πf₀)

Analog Devices provides these standard conversions. [Ref. 20]

Keysight uses equivalent equations in phase-noise analyzers. [Ref. 21]

A Useful but Counter-Intuitive Result

Ideal frequency multiplication worsens phase noise by 20log(M), but the carrier frequency also rises by M.

Therefore, ideal multiplication can leave time jitter approximately unchanged.

Phase jitter increases. Carrier frequency increases by the same ratio.

This distinction is important for data-converter clocking. Real multipliers still add their own noise.

20 fs at 20 GHz Is Already a Very Small Phase Angle

For σt = 20 fs and f₀ = 20 GHz, the RMS phase error is: σφ = 2πf₀σt.

Therefore, σφ ≈ 0.00251 rad, or approximately 0.144° RMS.

The ADF4382A specifies 20 fs integrated RMS jitter at 20 GHz. [Ref. 4]

That illustrates how demanding modern clock systems have become.

Distributed Phased Arrays Add Another Layer: Noise Correlation

This is where PLL architecture becomes especially interesting.

A common reference oscillator feeds many distributed PLLs. Its noise is correlated across the array.

Distributed PLL and VCO noise can remain largely uncorrelated.

Analog Devices models these effects separately. [Ref. 22]

That distinction changes array-level phase-noise scaling.

Uncorrelated PLL Noise Can Improve When Channels Combine

ADI measured multiple coherently combined transceiver outputs.

The uncorrelated contribution improved approximately with 10log₁₀(Nchannels) in the demonstrated case. [Ref. 22]

For four channels: 10log₁₀(4) = 6.02 dB

But common reference noise does not receive that benefit. It remains correlated. This makes the master reference increasingly important in large arrays.

A Large Array Can Eventually Become Reference-Noise Limited

As more channels combine, distributed uncorrelated noise averages downward. The shared reference contribution does not.

ADI's phased-array model shows this transition directly. [Ref. 22]

For very large arrays, the reference network can dominate. That means “one excellent PLL per channel” is not enough.

The Distribution Network Can Become the Hidden Phase-Noise Bottleneck

Reference fanout devices add their own noise. Clock PLLs add another transfer function. Amplifiers contribute residual noise.

ADI demonstrates significant differences between distribution architectures. [Ref. 22]

So phase-noise budgeting must include the complete clock tree.

A Current 2026 Beamforming Architecture Shows This Clearly

Analog Devices' 2026 Quad-Apollo platform supports 16 transmit and 16 receive channels. It targets X-band direct-RF digital beamforming. [Ref. 23]

A single high-stability reference forms the timing foundation. Low-jitter clock distribution maintains coherent timing across the converters.

That is exactly where PLL phase noise becomes array architecture.

Current Synthesizers Are Being Built for This Problem

The ADF4382A supports multichip phase alignment. It also provides sub-picosecond output-delay adjustment steps. [Ref. 4]

Its temperature propagation-delay coefficient is approximately 0.06 ps/°C.

Those capabilities reflect modern phased-array synchronization requirements.

Frequency accuracy alone is no longer enough.

PLL Phase Noise Is Also an RF PCB Problem

The synthesizer IC may be excellent but the assembled board can still be poor.

Phase-noise degradation can enter through:

• noisy power rails

• poor Return Paths

• reference coupling

• VCO tuning-line contamination

• output-to-input feedback

• digital clock coupling

• inadequate shielding

Analog Devices explicitly warns against reference-to-output crosstalk in PLL layouts. [Ref. 9]

Altium and Allegro Should Treat PLL Zones Differently

Do not route the PLL like ordinary mixed-signal logic. Create controlled physical zones for:

• reference input

• charge pump

• loop filter

• VCO supply

• RF output

• digital SPI

Keep the RF output away from the reference input. A tiny feedback path can become an unwanted spur mechanism.

The Loop Filter Is Not Just Three Passive Components

Its resistors generate thermal noise. Its capacitors carry dielectric imperfections. Its layout creates parasitic capacitance and inductance.

The VCO tuning node sees all of this. Therefore, loop-filter placement belongs in SI/PI review.

HFSS and CST Still Have a Role Here

PLL loop dynamics belong mainly in circuit simulation.

But HFSS or CST tools help evaluate:

• output-to-input coupling

• shielding structures

• reference-line coupling

• via transitions

• package interconnects

At 20–40 GHz, RF coupling paths become physically small. A digital-looking trace can become an RF feedback structure.

Do Not Use One Phase-Noise Number

A statement like “Phase noise = −100 dBc/Hz” is incomplete.

Phase noise must include the offset frequency.

Examples:

−80 dBc/Hz @ 1 kHz

−105 dBc/Hz @ 100 kHz

−135 dBc/Hz @ 10 MHz

These values describe different system mechanisms.

Close-In, Mid-Offset, and Far-Out Noise Do Different Jobs

Close-in noise

Often dominated by:

• reference oscillator

• flicker noise

• slow supply modulation

This region matters greatly to Doppler and coherent sensing.

Mid-offset noise

Often dominated by:

• PLL FOM

• PFD

• charge pump

• loop-bandwidth trade-offs

This is where N and fPFD become powerful design levers.

Far-out noise

Often dominated by:

• VCO

• output buffer

• multiplier additive noise

• broadband floor

Different applications care about different regions.

The Strategic Engineering Solution

Top-tier RF teams should design the entire LO noise budget, not merely select a “low-phase-noise PLL.”

1. Start With the System Phase-Noise Mask

Define requirements versus offset frequency. Do not begin with one integrated jitter number.

For Radar, emphasize close-in offsets.

For converters, integrated jitter may dominate.

For communications, include EVM and reciprocal mixing.

2. Choose the Highest Practical PFD Frequency

At fixed output frequency, higher fPFD reduces N. This improves in-band PLL noise.

Analog Devices explicitly recommends using the highest feasible PFD frequency, but verify divider limits and spur behaviour. [Ref. 3]

3. Separate Reference Noise From PLL FOM

Remember:

Reference contribution → 20log(N)

while:

PLL floor → FOM + 10log(fPFD) + 20log(N)

Do not claim a full 6 dB PLL improvement when N halves.

If fPFD doubled simultaneously, the ideal PLL-floor gain is about 3 dB. That distinction prevents incorrect architecture comparisons.

4. Optimize Loop Bandwidth From Real Noise Curves

Import measured or vendor data for:

• reference oscillator

• VCO

• PLL

• loop filter

Find their crossover.

Then evaluate:

• integrated jitter

• lock time

• spurs

• phase margin

TI recommends crossover-based bandwidth as a useful starting point. [Ref. 8]

5. Include Fractional and Integer-Boundary Spurs

Do not optimize phase-noise floor alone. Run every required channel frequency.

Search for problematic fractional states. Move the reference frequency where necessary.

Analog Devices recommends frequency planning for integer-boundary spur avoidance. [Ref. 1]

6. Budget Every Frequency Multiplier

For each multiplier, ΔLPN ≥ 20log(M).

Then add its residual phase noise.

A x4 mm-Wave multiplier costs at least 12.04 dB before implementation noise.

Do not discover this after selecting the synthesizer.

7. Design the Power Rails as Part of the PLL

Use noise spectral density. Do not judge an LDO from RMS voltage alone.

Pay particular attention to:

• VCO supply

• PLL analog rail

• charge-pump supply

• reference oscillator rail

Analog Devices identifies these rails as phase-sensitive nodes. [Ref. 11]

8. Protect the VCO Tuning Node

Keep it:

• short

• quiet

• shielded

• away from digital clocks

• away from switching power

Do not place test pads casually. Their capacitance and pickup can alter the loop.

9. Simulate the Complete Frequency Plan

Use ADIsimPLL, PLLatinum Sim, or equivalent tools.

Include:

• N

• PFD frequency

• loop bandwidth

• charge-pump current

• VCO Kv

• reference phase noise

Then validate the real hardware. Simulation should predict trends. Measurement remains the final authority.

10. Measure Phase Noise at Relevant Offsets

A spectrum analyzer trace may be insufficient. Use dedicated phase-noise measurement where needed. Integrate over the system-relevant bandwidth.

Keysight instruments report spot noise, integrated noise, RMS phase, and jitter. [Ref. 21]

The integration limits must match the application.

The 5G Infrastructure Consequence

Massive MIMO requires coherent RF channels.

LO noise directly contributes to:

• EVM

• adjacent-channel performance

• channel coherence

• calibration stability

Open RAN hardware also concentrates many synthesizers near antennas.

Reference-distribution architecture therefore becomes a scalability problem.

The Radar Consequence

Radar often values close-in noise more than integrated jitter. Weak Doppler targets can sit beside strong static returns.

Analog Devices emphasizes this requirement for high-clutter Radar systems. [Ref. 16]

So “20 fs jitter” alone may not answer the Radar question. You still need the spot phase-noise envelope.

The Satellite Communications Consequence

Ground stations often encounter strong neighbouring carriers. LO phase noise can degrade receiver selectivity. It can also contribute to uplink spectral regrowth.

For coherent phased terminals, channel LO stability matters additionally.

The reference-distribution strategy should therefore enter G/T and EIRP reviews.

The Aerospace & Defense Consequence

EW and Radar systems often require:

• low close-in phase noise

• fast frequency hopping

• low spurious content

• deterministic phase

Those requirements compete. A wider loop accelerates locking. A narrower loop may improve specific noise regions.

The best synthesizer setting therefore depends on mission mode.

The B2B Procurement Implication

A specification saying: “Low-phase-noise LO required” is inadequate.

A serious procurement requirement should include:

• carrier frequency

• phase noise versus offset

• integrated jitter limits

• PFD frequency

• reference requirements

• fractional-spur limits

• reference-spur limits

• lock time

• frequency-hopping behaviour

• temperature range

For Phased Arrays, also request:

• deterministic phase

• channel synchronization

• phase versus temperature

• common-reference architecture

For Radar, add:

• close-in noise mask

• chirp phase noise

• residual FM

For 5G, add:

• EVM contribution

• ACLR impact

• multichannel coherence

The Executive Takeaway

PLL multiplication obeys unforgiving mathematics.

Inside the loop:

LREF,OUT ≈ LREF + 20log₁₀(N)

So:

N = 120 → +41.58 dB

N = 60 → +35.56 dB

The reference contribution improves 6.02 dB, but the synthesizer's own white-noise floor follows:

LPLL ≈ FOM + 10log(fPFD) + 20log(N)

Therefore, doubling fPFD while halving N improves that term ≈ 3.01 dB.

Then loop bandwidth decides which noise source dominates, the reference path behaves roughly low-pass, the VCO contribution behaves roughly high-pass.

Any downstream multiplier then adds 20log(M) again.

So the real design question is not:

“How clean is my reference oscillator?”

It is:

“What does the complete LO architecture do to that reference?”

Because at mm-Wave:

frequency multiplication is also noise multiplication.

Multiply a reference by 120, and its phase noise can worsen by 41.6 dB.

At mm-Wave, frequency synthesis can destroy spectral purity surprisingly quickly.

That penalty directly affects Radar, Massive MIMO, Open RAN, and SatCom hardware. The mechanism is fundamental, but the design consequences are often misunderstood.

A clean reference is necessary. It is not sufficient.

The Core Physics: Frequency Multiplication Multiplies Phase Error

For an ideal frequency multiplication ratio N:

fOUT = N · fREF

The output phase becomes:

φOUT(t) = NφREF(t)

Therefore, reference phase-noise power scales approximately as:

LOUT(fm) ≈ LREF(fm) + 20log₁₀(N)

Analog Devices explicitly identifies this 20log(N) multiplication inside PLL bandwidth. [Ref. 1]

That relationship is one of the most important PLL design equations.

What Does 20log(N) Actually Mean?

Consider several multiplication ratios.