Phase-Bit Quantisation in Phased Arrays, RIS Metasurface, and RF Beamforming Hardware

Why more phase bits improve much more than peak antenna gain

RF ENGINEERING AND TECHNOLOGY

Dr Hadumanro Malau, AFHEA

10/15/202611 min read

IEEE-published analysis likewise reports below 0.3 dB beyond three bits. [Ref. 2]. That creates the first major engineering lesson.

If peak gain is your only metric, three bits already look excellent.

But peak gain is rarely the hardest phased-array requirement.

One Important Qualification

The sinc-squared values are average first-order estimates. They are not universal losses for every beam direction.

Quantisation error is deterministic across a real aperture. Some steering angles align naturally with available phase states.

Analog Devices shows zero quantisation error at particular scan angles. For its example, 30° steering produces zero quantisation error. Other angles produce strongly periodic errors. [Ref. 1]

Those errors create completely different radiation behaviour.

Key Point 1: Main-Beam Loss Is Usually Not the Real Problem

Phase quantisation does not simply reduce coherent gain. It changes the spatial distribution of radiation.

The residual phase error can be decomposed conceptually into:

coherent offset
spatial gradient
periodic error
random residual error

Each component creates a different system consequence.

A gradient moves the beam. Periodic errors generate quantisation lobes. Random errors raise the sidelobe floor.

Quantisation Lobes Can Dominate the Design

Analog Devices analyzed a 100-element phased array using digital phase shifters. [Ref. 1]

Its worst-case 2-bit quantisation sidelobe approached −7.5 dB. That is dramatically worse than the −0.91 dB gain penalty.

Analog Devices also found roughly 6 dB QSLL improvement per added bit.

Following that approximate trend:

2-bit → about −7.5 dB
3-bit → about −13.5 dB
4-bit → about −19.5 dB
5-bit → about −25.5 dB
6-bit → about −31.5 dB

Those values depend on geometry, tapering, and scan state.

But the trend exposes the real reason for extra bits.

More bits increasingly buy spatial cleanliness, not headline gain.

Why Quantisation Lobes Appear

Suppose the ideal aperture needs a smooth phase progression. Digital hardware replaces that ramp with a staircase.

The phase error therefore becomes spatially periodic.

Spatial periodicity creates spatial harmonics.

Those harmonics appear as unwanted beams.

A recent mixed-resolution study demonstrates these periodic phase-error patterns directly. The same study shows scan angle strongly changes quantisation behaviour. [Ref. 3]

So phase resolution cannot be evaluated at broadside alone.

A Phase-Bit Specification Without Scan Angle Is Incomplete

For a λ/2 linear array, ideal progressive phase follows:

ψ = π sinθ₀

Every requested steering angle creates another required phase gradient. The digital phase states approximate that gradient differently. Some angles produce very regular quantisation sequences. Others distribute phase error more favourably.

Therefore, quantisation performance is beam-state dependent.

That becomes critical when designing beam codebooks.

Nulling Can Demand More Bits Than Beamforming Gain

A broad main beam tolerates moderate phase error, a deep adaptive null does not.

Null formation requires near-perfect destructive interference. Tiny phase errors leave residual energy.

Therefore, three bits can appear excellent for gain. However, the same three bits can disappoint during interference cancellation.

This is particularly relevant in:

AESA Radar
electronic warfare
multi-user Massive MIMO
adaptive SatCom terminals

The correct bit depth comes from the spatial dynamic-range requirement.

Beam Pointing Also Behaves Differently

Phase quantisation perturbs the intended aperture gradient. The resulting beam can shift from its commanded direction.

A 2026 one-bit RIS study reported pointing-error challenges during wide scanning. Its optimized 14 × 14 architecture maintained under 2° pointing error. [Ref. 4]

That result required explicit codebook optimization.

Hardware resolution alone did not solve the beamforming problem.

Key Point 2: Nominal Bit Depth Is Not Actual Phase Accuracy

A 6-bit phase shifter means 64 nominal phase states. It does not guarantee 5.625° absolute accuracy.

Real phase states contain:

process variation
frequency dependence
temperature drift
amplitude-phase coupling
package parasitics
PCB feed error

This distinction is routinely missed in array specifications.

Current 2026 Hardware Demonstrates the Industry Direction

Qorvo's current AWMF-0239 operates from 27.5 to 31 GHz. It provides 6-bit phase control with 5.625° LSB resolution. [Ref. 5]

The device targets dual-polarized Ka-band SATCOM phased arrays. It also includes temperature compensation and telemetry functions.

Those features reveal something important.

Modern BFIC design is not chasing phase resolution alone. It is chasing repeatable phase resolution over operating conditions.

Another 2026 SATCOM Example Repeats the Pattern

Qorvo's AWMF-0238 covers approximately 17.7 to 21.2 GHz. [Ref. 6]

It also provides 6-bit phase control with 5.625° steps. The IC includes gain compensation and temperature reporting.

Again, phase resolution arrives alongside calibration-oriented hardware.

That is not accidental.

Analog Devices Shows Why Calibration Becomes Necessary

The ADAR1000 provides approximately 2.8° phase resolution across X/Ku bands. [Ref. 7]

However, channel and device variations must be compensated in practice. Analog Devices explicitly recommends adjusting I/Q values between individual devices. [Ref. 8]

So the usable resolution depends on calibration quality.

This creates another key principle.

Digital resolution is not the same as calibrated RF accuracy.

Quantisation Should Be Compared Against the Entire Error Budget

A useful array-level model is:

σ²TOTAL ≈ σ²Q + σ²BFIC + σ²FEED + σ²TEMP + σ²CAL

where: σQ is phase quantisation error.

Suppose non-quantisation RMS phase error totals: 5°.

For 4-bit control:

σQ ≈ 6.50°

Therefore:

σTOTAL ≈ √(6.50² + 5²)

giving approximately: 8.2° RMS.

Now use 6-bit control:

σQ ≈ 1.62°

Therefore:

σTOTAL ≈ 5.26° RMS

The improvement is meaningful. But the 5° hardware floor now dominates.

This Is Where More Bits Produce Diminishing Returns

If calibration uncertainty remains 8°, adding an eighth phase bit solves almost nothing. The system is not quantisation limited. It is calibration limited.

The next engineering investment should target:

temperature compensation
PCB phase matching
Dk tolerance
package variation
OTA calibration

Not necessarily another digital control bit.

The Calibration Burden Also Grows Exponentially

A B-bit phase shifter contains: 2ᴮ states

Therefore:

3 bits → 8 states
4 bits → 16 states
5 bits → 32 states
6 bits → 64 states
7 bits → 128 states

Now consider a 64-channel BFIC architecture.

Brute-force 6-bit characterization requires 64 × 64 = 4,096 channel-state measurements at one frequency and temperature.

Across five frequencies and five temperatures, 102,400 calibration points.

That excludes gain-control states entirely.

This is why intelligent calibration architecture matters.

More Bits Can Also Increase Implementation Cost

Digital phase shifters require additional switching structures. More states also require greater control and characterization complexity.

Classical antenna literature recognizes this gain-versus-complexity trade. [Ref. 9]

Practical phase-shifter architectures can also introduce insertion loss. For example, Qorvo's historical 5-bit device exhibited substantial RF insertion loss. [Ref. 10]

That number is architecture-specific.

The broader lesson remains valid:

Phase resolution cannot be optimized independently from RF loss.

A BFIC Is an Amplitude-and-Phase System

Switching between phase states can also change amplitude. That produces phase-dependent gain ripple.

A perfect phase code with varying amplitude still distorts the aperture.

Therefore, characterize A(state, f, T) and φ(state, f, T) simultaneously.

Do not build calibration tables from phase alone.

Key Point 3: RIS Quantisation Makes This Problem Even More Visible

Reconfigurable Intelligent Surfaces often prioritize low-cost unit cells. That makes 1-bit control especially attractive.

Each cell then provides only two reflection states. Typically, those states differ by approximately 180°.

The economic advantage is obvious.

The electromagnetic compromise is equally real.

One-Bit RIS Creates Quantisation Beams

IEEE analysis identifies an unavoidable quantisation beam in conventional 1-bit RIS. [Ref. 11]

The authors analytically predicted the unwanted beam directions. Codebook optimization then reduced their negative impact. That is directly analogous to quantisation lobes in active phased arrays.

The hardware architecture differs.

The spatial sampling physics does not.

A 2026 One-Bit RIS Paper Demonstrates Practical Scalability

A 2026 IEEE design operates around 3.384 GHz in 3GPP n78. [Ref. 12]

Its 8 × 10 array uses RF switches and delay lines. Each unit cell provides approximately 180° reflection-phase switching. Measured results demonstrated programmable beam steering.

So one-bit RIS is unquestionably practical.

But practical does not mean electromagnetically equivalent to continuous phase.

Two-Bit RIS Adds Four Phase States

A 2026 IEEE 6G RIS uses four digital reflection states. [Ref. 13]

Adjacent phase states differ by approximately 90° ±15°. The demonstrated surface contains 24 × 24 elements. The researchers report improved pointing and sidelobe suppression over 1-bit control.

This illustrates the core system trade.

Two bits cost more, but buy far better spatial control.

One-Bit RIS Can Still Be Valuable

Low phase resolution can be acceptable when priorities include:

low unit-cell cost
low controller complexity
reduced wiring
very large apertures
coverage enhancement

A 2025 IEEE system repurposed RFID tags into one-bit RIS elements. Its six surfaces contained 2,418 total reconfigurable cells. The measured deployment achieved substantial signal-strength improvement. [Ref. 14]

The lesson is not that one-bit architectures are poor.

The lesson is that their system objective differs.

RIS Phase Resolution Should Follow the Deployment Objective

For simple coverage redirection, 1-bit may be economically compelling.

For cleaner beam steering, 2-bit becomes substantially stronger.

For precise multi-user beams, higher resolution becomes increasingly attractive. But controller complexity, switching loss, and power also increase.

The optimum is therefore application-specific.

Massive MIMO Has a Similar Trade-Off

Hybrid beamforming uses fewer RF chains than digital beamforming. Analog phase shifters then control the antenna aperture. Finite resolution reduces beamforming accuracy.

IEEE finite-phase-shifter analysis shows resulting SINR degradation. At three bits and above, average gain penalty becomes small. [Ref. 2]

Yet multi-user interference may remain more demanding.

That distinction matters for Open RAN radio architecture.

Radar Usually Cares More About Sidelobes and Nulls

A Radar beam does not merely need peak gain. It needs spatial dynamic range.

Quantisation lobes can interact with:

clutter
jammers
multipath
adjacent targets
sidelobe blanking

A −7.5 dB quantisation lobe would be unacceptable frequently.

That explains why modern AESA BFICs commonly use higher resolution.

Current X-Band BFICs Commonly Reach Six Bits

Qorvo's current AWS-0101 supports four radiating elements. It provides 6-bit phase and gain control for AESA Radar. The architecture supports both transmit and dual receive beams. [Ref. 15]

Again, the motivation extends beyond peak gain.

Higher resolution improves beam shaping and spatial control.

SatCom Needs Accuracy Across Scan and Polarization

LEO terminals constantly change steering angle. Every beam state produces another phase-quantisation pattern.

Dual-polarized arrays add additional calibration complexity.

At low elevation, array margins are already reduced. Quantisation errors therefore consume valuable link-budget margin.

This is why phase bits belong inside the EIRP and G/T budgets.

Phase Quantisation Also Interacts With Frequency

Conventional phase shifters approximate steering at one frequency. Wideband operation introduces beam squint. Analog Devices explains this frequency-dependent steering error directly. [Ref. 16]

More phase bits do not remove beam squint. They only improve phase-state granularity.

This distinction is critical.

True Time Delay Solves a Different Problem

A true-time-delay system controls τ instead of only φ.

Since φ = 2πfτ, the correct phase naturally changes with frequency. That suppresses beam squint.

But digital TTD hardware still has finite delay resolution.

Current TTD Hardware Demonstrates the Difference

Analog Devices' ADAR4001 operates from 2 to 18 GHz. [Ref. 17]

It uses true time delay for beam-squint-free wideband operation. Its programmable delay resolution reaches 2 ps or 4 ps.

At 18 GHz, 2 ps ≈ 13° phase equivalent, which Analog Devices also reports. [Ref. 18]

TTD therefore eliminates frequency-dependent steering error.

It does not provide mathematically continuous delay.

This Creates a Better Architecture Question

Do not ask, “Phase shifter or TTD?”

Ask, “Which error dominates my operational bandwidth?”

For narrowband systems, phase-bit quantisation may dominate.

For wideband systems, beam squint may dominate.

For demanding systems, both can matter.

That is why hybrid PS-plus-TTD architectures remain compelling.

The Strategic Engineering Solution

Top-tier RF teams should design a phase-error budget.

Do not choose bit depth from competitor datasheets.

1. Start From Required Spatial Performance

Define:

allowable gain loss
sidelobe requirement
null depth
pointing accuracy
scan volume
bandwidth

Only then choose phase resolution.

2. Convert Bits Into Actual Phase Error

For each candidate:

Δφ = 360° / 2ᴮ

and:

σQ = Δφ/√12

Do not compare bit numbers alone.

Compare the resulting error distribution.

3. Evaluate Quantisation Lobes Across Scan

Do not measure broadside only.

Sweep θ × φ × frequency and record the worst quantisation sidelobe.

Analog Devices shows these lobes vary strongly with steering angle. [Ref. 1]

That should be part of every BFIC evaluation.

4. Model the Real Embedded Element Patterns

Quantisation errors interact with element radiation.

Use HFSS or CST Microwave Studio for:

embedded patterns
mutual coupling
polarization
active impedance

Then apply quantized beamforming weights.

Ideal isotropic-element simulations are not sufficient.

5. Include Measured BFIC State Data

Replace ideal states with measured gain(state) and phase(state) across frequency.

The resulting array model becomes much more realistic.

SystemVue can also incorporate measured beamformer behaviour.

Analog Devices provides measured-data beamformer modelling for ADAR1000. [Ref. 7]

6. Calibrate Across Temperature

Phase state changes with temperature.

PCB feed phase changes too.

PA and LNA response also moves.

The calibration database therefore needs thermal dimensions.

Modern BFICs increasingly include temperature telemetry for this reason. [Ref. 5]

7. Optimize the Codebook, Not Merely the Hardware

Nearest-phase rounding is simple. However, it is not always optimal.

Phase offsets can reduce quantisation degradation.

Published phased-array research demonstrates this behavior. [Ref. 19]

RIS research also uses codebook optimization to suppress quantisation beams. [Ref. 11]

Software can recover performance from finite hardware states.

8. Separate Gain Requirements From Sidelobe Requirements

This is critical.

Three bits may satisfy peak-gain requirements.

Five bits may be required for spatial purity.

Six bits may be justified by deep-null requirements.

One number cannot represent every design objective.

9. Stop Increasing Bits Once Another Error Dominates

Compare σQ against:

σCAL

σPCB

σTEMP

σIC

If quantisation is already much smaller, another bit produces little system benefit.

Invest engineering effort where the error budget is largest.

10. Measure OTA With Real Beam States

Measure:

realized gain
EIRP
sidelobe levels
pointing error
null depth
polarization
EVM or SINR where relevant

Use actual production beam codes.

Do not characterize only ideal simulation weights.

The Hardware Layout Still Matters

Phase resolution can be perfect digitally.

A poorly matched PCB can destroy that advantage.

Feed-length error creates deterministic phase offsets.

Dk tolerance creates frequency-dependent phase drift.

Copper roughness changes loss and effective propagation.

Connector transitions add channel-to-channel variation.

So Altium or Allegro phase matching remains important.

At mm-Wave, Millimetres Become Degrees

The propagation phase is: φ = βl.

Therefore, Δφ = βΔl.

At higher frequencies, small routing errors produce larger phase errors.

A 6-bit BFIC cannot repair unlimited PCB mismatch.

The RF stack-up and calibration architecture must work together.

Do Not Ignore Amplitude Quantisation Either

Modern BFICs often quantize both gain and phase.

For example, AWMF-0239 provides 6-bit phase and gain control. Its phase LSB is 5.625°. Its gain LSB is 0.25 dB. [Ref. 5]

The aperture therefore contains two independent digital staircases.

Both influence the final beam pattern.

The B2B Procurement Implication

A supplier statement saying, “6-bit beamforming”, is incomplete.

Request:

nominal phase LSB
RMS phase error
phase error versus frequency
phase error versus temperature
amplitude ripple versus phase state
insertion loss
calibration methodology
beam-switching latency
measured sidelobes
measured pointing accuracy

For phased arrays, request these values OTA.

For RIS, Ask Different Questions

Do not ask only, “How many phase bits?”.

Ask:

reflection magnitude per state
actual phase separation
bandwidth per state
switching speed
unit-cell loss
codebook method
unwanted quantisation beams

A four-state RIS with poor phase accuracy may underperform.

Bit count alone does not guarantee four useful states.

The 1-Bit Versus 2-Bit RIS Decision Is Especially Important

One-bit hardware minimizes cell complexity. But IEEE research confirms unavoidable quantisation-beam behavior. [Ref. 11]

Two-bit hardware provides four controllable phase states.

A 2026 design demonstrated improved pointing and sidelobe behavior. [Ref. 13]

That is a genuine engineering trade.

Not a marketing preference.

The Practical Bit-Depth Decision

1-bit

Useful for extremely low-cost binary RIS architectures.

Average ideal quantisation penalty ≈ 3.92 dB.

Spatial artifacts can be severe.

2-bit

Only four phase states.

Average ideal gain penalty ≈ 0.91 dB.

But worst quantisation lobes can remain relatively high. [Ref. 1]

3-bit

Eight phase states.

Average ideal loss ≈ 0.22 dB.

Often acceptable when peak gain dominates.

4-bit

Sixteen phase states.

Average ideal loss ≈ 0.056 dB.

A strong compromise for many conventional arrays.

5-bit

Thirty-two phase states.

Average ideal loss ≈ 0.014 dB.

Increasingly useful for sidelobes, nulls, and calibration.

6-bit

Sixty-four phase states.

Average ideal loss ≈ 0.0035 dB.

Current high-performance BFICs commonly use this resolution. [Ref. 5]

At this point, other hardware errors often dominate.

The Summary Takeaway

For B-bit phase control:

Δφ = 360°/2ᴮ

and:

ηq ≈ [sin(π/2ᴮ)/(π/2ᴮ)]²

That gives approximately:

1-bit → −3.92 dB

2-bit → −0.91 dB

3-bit → −0.22 dB

4-bit → −0.056 dB

So phase quantisation becomes almost irrelevant for peak gain quickly.

But that is not the full engineering story.

Analog Devices shows quantisation sidelobes improve roughly 6 dB per bit. Its 2-bit example reaches roughly −7.5 dB worst-case QSLL. [Ref. 1]

Current 2026 Ka-band BFICs therefore use 6-bit phase control. [Ref. 5]

Current RIS research still explores both 1-bit and 2-bit architectures. [Ref. 12] [Ref. 13]

The optimum therefore depends on what the system must preserve, not merely maximum realized gain.

Three bits can be enough for gain.

More bits are often purchased for beam quality.

And once calibration error exceeds quantisation error:

another bit may buy almost nothing.

A 2-bit phase shifter can lose only 0.91 dB in average gain. Yet its quantisation lobes can sit only about 7.5 dB down. [Ref. 1]

That difference is where phase-bit specifications become dangerously misleading. Peak gain tells only one part of the beamforming story.

Radar, SatCom, Massive MIMO, and RIS systems need spatial purity too. They need controlled sidelobes, nulls, pointing accuracy, and coherent calibration.

Start With the Actual Quantisation Physics

A B-bit phase controller provides:

M = 2ᴮ phase states

Its ideal phase increment becomes:

Δφ = 360° / 2ᴮ

Nearest-state rounding produces maximum phase error:

|εφ,max| = Δφ / 2

Assuming uniformly distributed phase errors, the RMS error becomes:

σφ = Δφ / √12

That error directly perturbs coherent field addition.

The Phase Resolution Changes Quickly With Bit Depth