Decoupling Anti-Resonance in RF and High-Speed PCB Hardware

Adding another decoupling capacitor can increase PDN impedance instead of reducing it.

The failure mechanism is anti-resonance, not insufficient capacitance.

That distinction matters around PLLs, VCOs, beamformer ICs, LNAs, and ADC clocks. It also matters inside PA bias networks and high-current digital rails.

The design target is therefore not:

“Add as much capacitance as possible.”

It is:

“Keep PDN impedance below its target across the required spectrum.”

Keysight defines target impedance from allowable ripple divided by transient current. [Ref. 1]

Texas Instruments uses the same frequency-domain target-impedance methodology. [Ref. 2]

Start With the Real Capacitor

An ideal capacitor has: ZC = 1/(jωC)

A real mounted capacitor is closer to: Z(jω) = ESR + j(ωESL − 1/ωC)

Murata uses this same series RLC representation for real capacitors. [Ref. 3]

Its magnitude becomes: |Z| = √[ESR² + (ωESL − 1/ωC)²]

At low frequency: 1/ωC dominates

Near resonance: ωESL ≈ 1/ωC

Above resonance: ωESL dominates

Murata confirms capacitors become predominantly inductive above self-resonance [Ref. 4]. Keysight gives the same high-frequency capacitor behaviour in PDN analysis. [Ref. 5]

Self-Resonant Frequency Is the First Boundary

The self-resonant frequency is: fSR = 1/(2π√ESL·C)

Consider:

• C = 100 pF

• Effective ESL = 0.5 nH

Then: fSR ≈ 712 MHz

Below 712 MHz, this branch is mainly capacitive.

Near 712 MHz, impedance reaches its minimum.

Above 712 MHz, the branch becomes increasingly inductive.

And that 0.5 nH must include more than package ESL.

It can include:

• capacitor geometry

• pads

• vias

• spreading inductance

• Return Paths

That is where schematic-level capacitor selection starts becoming insufficient.

Mounting Inductance Can Move the Resonance Dramatically

Keep C = 100 pF, but change effective ESL.

0.2 nH: fSR ≈ 1.13 GHz

0.5 nH: fSR ≈ 712 MHz

1.0 nH: fSR ≈ 503 MHz

The capacitor value never changed, but the PCB changed its useful frequency range. This is why “100 pF” is not a complete RF decoupling specification.

TI explicitly treats capacitor placement through effective loop inductance. It also notes smaller ceramic capacitors typically have lower ESL. [Ref. 6]

Pain Point 1: Different Capacitors Can Create an Impedance Peak

Suppose two capacitor branches are connected in parallel. One capacitor may already be inductive and the other may still be capacitive. Their reactive currents can cancel. The combined network then produces parallel anti-resonance.

Unlike self-resonance, anti-resonance produces an impedance maximum.

Keysight distinguishes series-resonance minima from parallel-resonance maxima. [Ref. 7]

Siemens states different capacitor values can generate parallel-resonant impedance peaks. [Ref. 8]

Murata demonstrates the same effect using unequal capacitor values. [Ref. 4]

A Numerical Example Makes the Mechanism Clear

Consider two idealized mounted branches:

Branch 1

C₁ = 100 nF

L₁ = 0.5 nH

Its self-resonance is: fSR1 ≈ 22.5 MHz

Branch 2

C₂ = 1 nF

L₂ = 0.5 nH

Its self-resonance is: fSR2 ≈ 225 MHz

Now connect both branches in parallel. Between those resonances:

• the 100 nF branch becomes inductive

• the 1 nF branch remains capacitive

For two lossless series-LC branches: fAR ≈ (1/2π)√[(1/C₁ + 1/C₂)/(L₁ + L₂)]

For this example: fAR ≈ 160 MHz

That anti-resonance lies between both self-resonant frequencies. The exact peak magnitude depends strongly on ESR and layout loss. That detail matters enormously.

Low ESR Can Make the Peak Worse

Engineers usually associate low ESR with better capacitors. That is only partly true. Low ESR reduces minimum impedance near series resonance, but low damping can increase parallel-resonant Q.

Keysight recommends controlling ESR for flat-impedance PDN design. [Ref. 9]

TDK specifically uses selectable ESR to suppress decoupling anti-resonance. [Ref. 10]

That creates a counter-intuitive engineering truth:

The lowest-ESR capacitor is not always the best PDN choice.

Sometimes loss is useful. Controlled loss can suppress a dangerous impedance peak.

TDK Describes the Failure Mechanism Explicitly

TDK explains anti-resonance between capacitors with different self-resonances. [Ref. 10]

One capacitor operates inductively, another simultaneously operates capacitively. Their interaction creates a high-impedance parallel resonance.

TDK warns the resulting voltage disturbance can cause jitter and logic errors. In severe cases, the voltage excursion can threaten semiconductor reliability.

That is not theoretical SI/PI trivia. It is a system failure mechanism.

Murata Shows Why “One of Every Value” Can Be Dangerous

Traditional decoupling often used:

• 10 µF

• 1 µF

• 100 nF

• 10 nF

• 1 nF

The intention was broad frequency coverage, but that approach can create many resonance interactions.

Murata warns significantly different capacitances can create anti-resonant impedance peaks. The effect becomes stronger as PCB-pattern inductance increases. [Ref. 4]

Murata specifically compares 1000 pF and 1 µF in parallel. The simulated network develops anti-resonance between their self-resonances.

That is a three-decade capacitance spread, exactly the type engineers often add “for safety.”

Using Equal Values Can Sometimes Be Better

Murata also evaluates multiple capacitors with the same capacitance. Their SRFs remain aligned when mounting geometry is equivalent. Adding more identical capacitors then lowers total impedance. [Ref. 4]

Siemens reports the same qualitative behaviour. [Ref. 8]

That does not mean: “Always use one capacitor value.”

It means: “Do not stagger values blindly.”

The full PDN must decide the capacitor set.

Even Identical Capacitors Can Behave Differently After Layout

Suppose two identical 100 nF MLCCs are used. One sits 2 mm from the IC, and another sits 30 mm away.

Their component models may be identical, but their effective branch inductances are not. Now their installed resonances differ.

Murata notes different PCB patterns can create anti-resonance even with equal capacitance. [Ref. 4]

This is a critical layout lesson: Capacitor location is an electrical value.

Pain Point 2: Target Impedance Matters More Than Capacitor Count

The PDN design objective can be written: ZPDN(f) < ZTARGET

with: ZTARGET = ΔVALLOWABLE / ΔITRANSIENT

Keysight describes target impedance using allowable ripple and current step. [Ref. 1]

TI uses the same principle in its current Sitara PDN guidance. [Ref. 2]

AMD's 2026 Versal PCB guide also calculates target impedance from ripple tolerance. [Ref. 11]

A Simple Target-Impedance Example

Suppose a rail allows ΔV = 30 mV and experiences ΔI = 3 A.

Then, ZTARGET = 10 mΩ

That means every relevant resonance matters.

A PDN sitting at 5 mΩ for most frequencies can still fail. One anti-resonance reaching 40 mΩ can violate the power-integrity requirement.

The average impedance is irrelevant. The peak determines the failure risk.

Keysight Gives a Real 12 mΩ Example

Keysight uses:

• allowable ripple = 60 mV

• current step = 5 A

giving ZTARGET = 12 mΩ for its FPGA example. [Ref. 1]

Keysight then advocates flat impedance across frequency. The goal is avoiding high-Q resonances and rogue voltage waves.

That is far stronger than checking total capacitance.

The Industry Target Is Getting Harder

Modern IC rails operate at lower voltages. Transient current continues increasing. That pushes target impedance downward.

Siemens noted in 2025 that some modern targets fall below 1 mΩ. [Ref. 12]

At that level:

• via inductance matters

• spreading inductance matters

• package inductance matters

• capacitor placement matters

• plane geometry matters

A schematic BOM cannot predict compliance.

2026 AMD Guidance Reinforces This Point

AMD's June 2026 Versal guide defines explicit target impedance. AMD also warns capacitor mounting inductance limits effectiveness at high frequency. It recommends full board-level PDN simulation for verification. [Ref. 11]

That is the modern engineering direction:

simulate the installed PDN, not the capacitor list.

Board-Level Decoupling Has a Frequency Ceiling

At sufficiently high frequency, board capacitors stop dominating. Their ESL and mounting inductance become too large.

Siemens describes board decoupling transitioning toward package and on-die capacitance. Package inductance limits how high board-level decoupling remains effective. [Ref. 8]

TI likewise identifies a maximum frequency beyond practical board-decoupling control. [Ref. 2]

Beyond that point, the package becomes part of the PDN architecture.

This Matters Particularly for Beamformer ICs

A beamformer IC may contain:

• gain stages

• phase shifters

• digital control

• bias generators

• LO circuits

Those blocks create wideband transient currents. The local supply therefore sees multiple spectral demands. A narrow anti-resonance can selectively amplify one disturbance band.

The result can appear as:

• gain modulation

• phase modulation

• spur generation

• channel-to-channel error

The RF engineer may blame the antenna first, but the actual problem may sit on the power plane.

Pain Point 3: PDN Anti-Resonance Can Become RF Modulation

Supply noise is not necessarily confined to the supply rail. Sensitive RF blocks can convert it into signal degradation. PLLs are one obvious example.

Analog Devices notes modern PLL performance can become supply-noise limited. VCO supply variation produces unwanted frequency change through VCO pushing. [Ref. 13]

That converts PDN ripple into phase noise or spurious modulation.

A Quantified PLL Example

Analog Devices measured ADF4350 VCO pushing up to 5.55 MHz/V at one 4.4 GHz operating condition. [Ref. 13]

Another ADI measurement reported approximately 5.99 MHz/V around 4.4 GHz. [Ref. 14]

Now imagine an anti-resonant PDN peak generating 10 mV ripple at a sensitive frequency.

Using 5.55 MHz/V, the instantaneous frequency sensitivity becomes approximately: 55.5 kHz.

This is only a first-order sensitivity estimate. The PLL transfer function determines the final spectral response, but the coupling mechanism is real.

ADI Shows Supply Noise Can Change Measured Phase Noise

Analog Devices compared two LDOs on an ADF4350 supply. One produced roughly 27 µV RMS noise and another 9 µV RMS. [Ref. 13]

The noisier regulator measurably degraded PLL phase-noise performance. The quieter supply approached battery-powered performance.

That means the PDN impedance profile can become part of the LO phase-noise budget.

A VCO Rail Can Be Sensitive to Layout, Not Just Capacitance

Analog Devices documented a VCO spur problem caused by PCB routing. The VCO supply trace passed beneath the charge-pump supply. Additional capacitance did not solve that case. Rerouting the supply reduced the spur to a compliant level. [Ref. 15]

That is an excellent reminder.

Sometimes the PDN problem is coupling topology not insufficient capacitance.

PA Bias Networks Can Also Suffer Anti-Resonance

RF PA bias paths often combine several capacitances and different values are used across broad frequency ranges.

Murata explicitly warns different capacitors on FET bias lines can anti-resonate. Murata develops low-ESL silicon capacitors specifically for RFPA decoupling. Its solutions target suppression into hundreds of megahertz. [Ref. 16]

At PA currents, bias modulation can become:

• AM distortion

• AM-PM distortion

• IMD

• gain variation

That directly affects transmitter quality.

The RF Consequence Is Especially Important in Massive MIMO

One noisy PA bias rail may affect one channel. A shared noisy supply can affect many channels coherently. That difference matters.

Correlated supply modulation can create correlated channel error. That can disturb:

• beamforming amplitude

• beamforming phase

• EVM

• ACLR

• coherent EIRP

Antenna calibration cannot fully repair unstable supply behaviour.

Open RAN Makes PDN Architecture a Density Problem

Massive MIMO radios integrate many active channels. The RF electronics sit increasingly close to antenna elements. This reduces feeder loss. It also increases local power-density complexity.

Now PDN design must manage:

• PAs

• beamformers

• clocks

• converters

• FPGA/SoC rails

inside the same physical enclosure.

An anti-resonance peak can couple multiple subsystems unexpectedly.

Radar Adds a Different Excitation Mechanism

Radar current demand can be highly periodic. Transmit pulses may repeatedly excite one PDN resonance. If the pulse spectrum overlaps an anti-resonant peak, the network can ring.

Keysight warns transient activity can excite high-Q PDN resonances. The resulting “rogue waves” can exceed expected voltage noise. [Ref. 17]

This is why frequency-domain impedance predicts time-domain failures.

Frequency and Time Domains Tell the Same Story

Suppose a PDN has a sharp impedance peak at 100 MHz. Its corresponding oscillation period is 10 ns.

A transient edge can excite this mode. The rail then rings near that frequency, and a high-Q peak rings longer. A damped, flat impedance profile settles faster.

That is why Keysight promotes flat impedance rather than deep minima. [Ref. 1]

The Worst PDN Is Not Necessarily the Highest Average Impedance

Consider two hypothetical designs.

Design A

Impedance stays around 15 mΩ with minimal peaking.

Design B

Impedance falls to 2 mΩ, but peaks to 60 mΩ near 80 MHz.

If: ZTARGET = 20 mΩ

Design A passes and Design B fails.

Yet Design B may contain many more capacitors.

This is why “more decoupling” is a poor design metric.

ESR Is a Design Parameter, Not an Imperfection

At self-resonance, capacitive and inductive reactance cancel. The remaining minimum impedance approaches ESR.

Lower ESR gives deeper series-resonant minima, but very low ESR can also increase resonance Q.

Keysight's flat-Z guidance explicitly recommends selecting ESR intentionally. [Ref. 9]

TDK uses controlled ESR specifically to suppress anti-resonance. [Ref. 10]

A little loss can therefore improve system stability.

This Does Not Mean “Add Random Resistance”

Damping must be intentional.

Potential methods include:

• higher-ESR capacitor selection

• dedicated damping branches

• lossy bulk capacitance

• optimized VRM output impedance

• reduced inductive separation

The objective is: lower peak Q without raising broadband impedance excessively.

That is an optimization problem, not a universal resistor value.

Plane Capacitance Is Also Part of the Network

Closely spaced power-ground planes create distributed capacitance. Their geometry also creates resonant cavity behaviour.

Siemens includes inter-plane capacitance in advanced PDN modelling. [Ref. 8]

TI also includes inter-plane capacitance in its PDN hierarchy. [Ref. 2]

Therefore, capacitor-only simulation misses part of the network.

The PCB itself is a distributed component.

Plane Spreading Inductance Changes What the IC Actually Sees

A capacitor 50 mm away can have impressive datasheet impedance. However, the IC does not see the datasheet directly. It sees capacitor + mounting + planes + package.

Siemens calculates plane spreading and mounting inductance in PDN analysis. The impedance must be evaluated at the actual power pins. [Ref. 8]

That is the correct reference plane, not the capacitor pads.

Return Paths Matter Here Too

A decoupling capacitor supplies a current loop. The current leaves one terminal, it must return through the adjacent reference structure. Loop inductance determines high-frequency effectiveness.

Therefore:

• via separation

• plane adjacency

• cavity thickness

• fanout geometry

all matter. This is power integrity and return path engineering simultaneously.

A Small Geometric Change Can Beat a Larger Capacitor

Suppose a decap's effective loop inductance drops 1.0 nH → 0.4 nH.

At 100 MHz: XL = 2πfL, giving: 0.628 Ω → 0.251 Ω

The capacitance did not increase. The high-frequency branch improved by 60% inductive reactance reduction.

That is why placement can outperform extra capacitance.

Low ESL Becomes Critical at RF-Oriented Frequencies

Murata emphasizes ESL as the high-frequency limiting parameter. Changing capacitance alone does not overcome identical ESL above SRF. [Ref. 4]

For very high-frequency decoupling, package geometry becomes critical and mounting geometry becomes equally critical.

This is why 0201, reverse-geometry, three-terminal, and silicon capacitors exist.

Three-Terminal Capacitors Attack the Loop Differently

Three-terminal structures force current through the capacitor geometry. This can produce stronger high-frequency insertion loss than ordinary shunt MLCCs.

Murata specifically positions three-terminal capacitors for low-impedance power circuits. [Ref. 18]

Their benefit comes from feed-through current geometry.

That differs fundamentally from simply adding another two-terminal capacitor.

The Strategic Engineering Solution

Top-tier RF hardware teams should design a PDN impedance profile. They should not design a capacitor inventory.

1. Define ZTARGET First

Start with: ZTARGET = ΔV / ΔI

Define:

• allowable ripple

• transient current

• relevant frequency range

Keysight uses this exact target-impedance methodology. [Ref. 1]

AMD uses it in current 2026 FPGA guidance. [Ref. 11]

Without ZTARGET, there is no objective pass/fail criterion.

2. Define the Frequency Range of Interest

Do not say: “Low impedance everywhere.”

No PCB can accomplish that indefinitely.

Define: FMIN → FMAX

TI describes FMAX as the point board decoupling becomes ineffective. [Ref. 2]

Above this region, package and die decoupling dominate increasingly. That boundary is device dependent.

3. Use Actual Capacitor Models

Do not use C = 100 nF alone.

Use:

• C versus bias

• ESR versus frequency

• ESL

• SRF

• package model

• vendor S-parameters

Keysight explicitly distinguishes lumped RLC and S-parameter capacitor modelling. [Ref. 7]

For GHz-class analysis, measured models can be valuable.

4. Include DC-Bias Capacitance Loss

Class-II MLCC capacitance can change under DC bias. Therefore, nominal capacitance may not equal installed capacitance. This can move resonances.

It can also change anti-resonant frequency.

Use the capacitor's biased operating value. Do not trust only the case marking.

5. Extract Mounting Inductance

Include:

• pad geometry

• via diameter

• via spacing

• plane depth

• fanout path

TI explicitly uses loop inductance to quantify capacitor effectiveness. [Ref. 6]

If mounting dominates, a better capacitor alone will not solve the problem.

6. Model the Entire PDN

The simulation should include:

VRM → bulk → PCB planes → MLCCs → package → die

Siemens describes exactly this distributed hierarchy. [Ref. 19]

Board-level capacitor optimization without package effects can mislead. Especially near the board-to-package transition.

7. Avoid Blind Decade Stacking

Do not automatically use: 10 µF + 1 µF + 100 nF + 10 nF, because tradition says so.

Different SRFs can generate anti-resonance. [Ref. 4]

Use simulation to decide whether staggered values help. Sometimes repeated identical values produce a flatter result.

8. Intentionally Add Damping Where Needed

If a high-Q peak remains, consider damping.

Possible mechanisms include:

• appropriate ESR

• lossy bulk capacitor

• damping branch

• regulator impedance shaping

Keysight promotes flat impedance over very deep resonant valleys. [Ref. 1]

TDK demonstrates ESR-controlled anti-resonance suppression directly. [Ref. 10]

9. Optimize Placement Before Adding Quantity

Place critical capacitors near the relevant power pins. Minimize the complete current loop.

TI recommends close placement to minimize loop inductance. [Ref. 2]

For BGA devices, bottom-side placement can sometimes shorten effective current paths, but the complete escape geometry still requires extraction.

10. Simulate at the IC Pins

The impedance at the regulator is not enough. The capacitor-pad impedance is not enough.

Probe ZPDN(f), where the IC actually draws current.

Siemens' advanced decoupling evaluates impedance at device power-pin locations. [Ref. 8]

That should be the engineering signoff plane.

11. Measure the PDN

Simulation should not be the final step.

Measure board impedance using appropriate methods.

Options can include:

• 2-port shunt-through

• impedance analyzers

• VNA-based PDN measurements

The measurement needs very low noise floor.

Milliohm-level impedance is not a routine VNA measurement. Fixture and cable resistance can dominate.

12. Correlate Frequency and Time Domains

First measure: ZPDN(f). Then excite the rail with realistic transients. Check whether impedance peaks predict ringing.

A strong correlation increases confidence in the model.

If they disagree, inspect measurement setup and load model.

Altium or Allegro Must Carry More Than Capacitor Designators

The layout database should preserve:

• capacitor location

• orientation

• fanout

• via count

• power-plane connectivity

These are electrical properties.

Changing placement late in layout can invalidate the PI result.

A schematic-equivalent capacitor is not necessarily PDN-equivalent.

SI/PI Tools Should Drive Decoupling Selection

Use extracted-board analysis. Include real plane geometry.

Siemens HyperLynx explicitly models [Ref. 8]:

• capacitor location

• mounting parasitics

• inter-plane capacitance

• plane spreading inductance.

Keysight ADS likewise supports full VRM-to-load PDN simulation. [Ref. 20]

These tools can identify anti-resonance before fabrication.

HFSS or CST Have a Role at the Upper Frequency End

At sufficiently high frequency, the PCB behaves electromagnetically distributed. Vias, planes, packages, and cavities develop modes.

Murata notes electromagnetic simulation becomes important above hundreds of megahertz. [Ref. 21]

That is where full-wave tools become valuable.

Especially around:

• beamformer packages

• RFIC power cavities

• mmWave modules

• dense interposers

RF and PI Models Must Describe the Same Hardware

This principle keeps appearing throughout RF design.

The antenna model should match the PCB.

The thermal model should match the RF geometry.

The PDN model should match the actual stack-up.

Otherwise, correlation becomes parameter fitting.

That is not predictive engineering.

The Aerospace & Defense Consequence

A defense RF board can meet RF performance at nominal conditions. Yet a PDN resonance may appear under another operating mode.

Radar pulse patterns can excite specific frequencies.

Digital control blocks can change switching spectra.

MIL-STD-461 does not prescribe decoupling capacitor values.

But PDN resonances can worsen conducted and radiated noise margins.

Therefore, PDN design belongs inside EMC risk review.

The Satellite Communications Consequence

SatCom payload and Ground-station electronics combine:

• PLLs

• beamformers

• ADC/DAC clocks

• PAs

• high-speed digital processing

Each has different PDN sensitivity.

A single shared anti-resonance can couple subsystem noise.

For LEO payloads, board area and mass also constrain decoupling. That makes optimized capacitance more valuable than capacitor quantity.

Rad-Hard layout does not solve PDN anti-resonance. Multipactor mitigation does not solve it either.

These are independent reliability mechanisms.

Rigid-Flex RF Creates Additional PDN Geometry

Rigid-flex systems can change:

• plane spacing

• conductor width

• return path

• power-path inductance

at the rigid-flex transition.

Those changes alter PDN impedance. A bypass capacitor near a flex transition can therefore behave differently.

Rigid-flex RF requires PI extraction across the physical transition. Do not treat the flex as an ideal wire.

The B2B Procurement Implication

A supplier statement saying: “We fitted all recommended decoupling capacitors”, is not evidence of power integrity.

Request instead:

• ZTARGET

• frequency range

• simulated ZPDN

• worst impedance peak

• capacitor models

• mounting inductance

• package model

• board stack-up

• measurement correlation

For RF modules, also request:

• PLL supply sensitivity

• PA bias ripple

• LO spur impact

• beamformer channel variation

For Massive MIMO, include channel-correlated supply modulation.

For Radar, include pulse-excited PDN ringing.

A 2025 Optimization Trend Is Already Emerging

Modern PDN tools increasingly optimize capacitor count automatically.

Siemens described a 2025 genetic-algorithm PDN optimizer. Its objective includes meeting target impedance with fewer capacitors. [Ref. 12]

This reflects an important industry shift.

The question is no longer: “How many capacitors can we place?”

It is: “What is the minimum robust network meeting ZTARGET?”

Why Fewer Capacitors Can Sometimes Be Better

Removing a capacitor can eliminate an anti-resonant interaction.

It can also:

• reduce BOM

• free routing area

• remove solder joints

• simplify validation

Keysight's flat-impedance method specifically seeks minimum capacitor count. [Ref. 1]

The objective remains system impedance, not capacitor density.

The Summary Takeaway

A real capacitor is approximately: Z(jω) = ESR + j(ωESL − 1/ωC)

Its self-resonance is: fSR = 1/(2π√ESL·C)

For 100 pF + 0.5 nH, that becomes: fSR ≈ 712 MHz

Above that frequency, the branch behaves predominantly inductively.

Now place different capacitor values in parallel.

One branch can become inductive. Another remains capacitive. Their interaction can create an anti-resonant impedance peak

Murata and Siemens both document this behaviour directly. [Ref. 4], [Ref. 8]

The correct PDN objective is therefore: ZPDN(f) < ZTARGET,

not: maximum total capacitance

and not: maximum capacitor count

Keysight, TI, and AMD all use target-impedance-based PDN design. [Ref. 1], [Ref. 2], [Ref. 11]

So the better engineering question is not:

“How many decoupling capacitors did we place?”

It is:

“What impedance does the silicon actually see across frequency?”

Because in advanced RF hardware:

a decoupling capacitor can suppress noise or create its resonance.